The present invention generally relates to the generation of clock signals in a multi-channel architecture, such as a tester circuit, according to the preamble of the independent claims.
A multi-channel architecture generally comprises a main computer system and a plurality of individual channels. The multi-channel architecture distinguishes from other computer architectures in that the multi-channel architecture allows a functioning of each one of the plurality of individual channels independent of the other channels.
An important application of the multi-channel architecture is in testing applications for testing e.g. integrated circuits (IC's) or other electronic devices, such as the Hewlett-Packard HP 83000 Digital IC Test Systems. A typical testing unit comprises a tester circuit and a device under test (DUT), which can be an IC or any other electronic device. The tester circuit generally comprises a signal generating unit for generating and applying a stream of stimulus data (also called vector data) to the DUT, a signal receiving unit for receiving a response on the stream of stimulus data from the DUT, and a signal analyzing unit for comparing the response with an expected data stream. The tester circuit can thus draw conclusions about the properties and quality of the DUT.
In certain multi-channel architecture systems, data and signals are applied, received, provided, driven, or processed in any way in a so called period driven approach. This means that data is driven or sampled during a specific clock cycle defined as the period of time between successive rising edges of a periodic clock signal. The exact position in time within such a clock cycle, for example the moment when a certain action is to be started, is determined by a so-called edge delay which is referenced to the start of the respective clock cycle and associated to the drive or sample actions by the vectors. In particular, the period driven approach may be applied in tester systems for applying the stimulus data to the DUT and capturing the response. This means that data is driven or sampled during a clock cycle of the DUT.
In a tester multi-channel architecture such as a tester per pin architecture, each one of a plurality of signal pins of the DUT is usually connected to one channel of the tester circuit. Each channel contains a complete test processor comprising all necessary components for generating the stimulus data and/or expected data streams including edge delay generators that provide time marks at defined positions within a respective clock cycle.
FIG. 1 shows an example of a tester per pin architecture as known in the art, as an example for a multi-channel architecture applying the period driven approach. A tester 10 contains a central master clock generator 40 feeding a master clock signal 200 into a master clock gate 50. The master clock gate 50 is controlled by a change timing circuit 60 through a clock enable signal 220. An output of the master clock gate 50, a gated master clock 210, is distributed to a plurality of tester channels 20aa . . . 20zz along with the clock enable signal 220. The tester channels 20aa . . . 20zz are respectively connected to an individual pin of a DUT 70 through respective pin lines 300aa . . . 300zz. The tester channels 20aa . . . 20zz contain respective timing generators 30aa . . . 30zz, which are usually built up of an arbitrary number of edge delay generators using the gated master clock 210 for a generation of an edge.
Each respective clock cycle and each respective edge position used for testing the DUT 70 is derived from the centrally generated master clock 200 of a frequency that normally is an even multiple of the clock frequency of the DUT 70.
Each one of the timing generators 30aa . . . 30zz for generating edge delays use a first rising edge of the gated master clock 210 as a reference. The first edge is generated, usually after a programmable amount of clock cycles of the master clock 200 and an also programmable analog delay after that first master clock cycle, by gating the master clock 200 by means of the master clock gate 50, thus receiving the first rising edge of the gated master clock 210. The generation of an edge may then be repeated after a programmable amount of cycles of the master clock 200.
Once the generated edge delays are established, their relationship stays fixed as long as the master clock 200 is active. For some types of DUT 70 it is necessary, however, to reprogram the timing generators 30aa . . . 30zz during an execution of a test to change the position of the drive and sampling actions in the clock cycle.
In order to perform the reprogramming of the edge positions, the timing generators 30aa . . . 30zz output a ready-for-change signal 230 that is accumulated from all tester channels 20aa . . . 20zz, e.g. by using a WIRED-AND connection. The ready-for-change signal 230 is sent to the change timing circuit 60 requesting the gated master clock 210 to be stopped, so that the timing generators 30aa . . . 30zz can be reprogrammed. The change timing circuit 60 deactivates the clock enable signal 220 which stops the gated master clock 210 through the central master clock gate 50 and also instructs the timing generators 30a . . . 30zz to accept their new programming values and deactivate the ready-for-change signal 230. This, in turn, causes the change timing circuit 60 to restart the gated master clock 210 through the clock enable signal 220. In that way, a new first rising edge of the gated master clock 210 is generated as a new reference for the timing generators 30aa . . . 30zz.
The architecture of FIG. 1 has certain advantages such as an unmatched speed and accuracy. However, disadvantageous is that during the reprogramming of the timing generators 30aa . . . 30zz the gated master clock 210 needs to be turned off. This interrupts the stimulus data stream on all pin lines 300aa . . . 300zz of the DUT 70. DUTs 70 which e.g. use phase locked loop (PLL) circuits to generate an internal clock from an external reference clock will have to wait for a PLL lock after such an interruption. This severely limits the efficiency and throughput of the tester 10 and thus leads to an increase of the testing. expenditure.
A further problem occurs in the architecture of FIG. 1 when more than one DUT 70 is to be tested at the same time (a so called multi-site test). In order to save costs and to make optimal use of the tester 10, as many devices as possible should be tested in parallel. In an architecture allowing parallel testing, central resources of the tester 10 such as cabinets, computer, manipulator and controller are required only once.
The multi-site test challenges the traditional tester per pin architecture, because the devices to be tested can behave differently, due to production variance in speed or functional defects. Therefore, the need arises to follow different paths in the test execution flow for the differing DUTs. The test execution for a plurality of different DUTs should preferably be executed in parallel, so that the throughput advantage of multi-site testing is not lost to the need to execute different paths one at time. This ability involves edge delay reprogramming for one DUT while the other DUTs perform different operations at the same time. However, as soon as the gated master clock 210 is turned off by the change timing circuit 60 due to reprogramming, the other DUTs can not continue to operate undisturbed.